The purpose of the VCD Writer is to translate data from an SST2 Database to the VCD (Value Change Dump) file format. The VCD Writer provides two options for generating files. You can generate a VCD file for selected variables or generate VCD files for all recorded variables.

Select File>Write VCD>For Selected Variables to generate a VCD file only for selected variables. Select File>Write VCD>For All Recorded Variables to write out all the variables recorded in your SST2 Database.

Using the VCD Writer

In the Waveform Window, select some or all of the variables in the Names Pane. Variables can be selected from different files. If the same variable is selected more than once, it is only written once to the VCD file. After selecting the variables, choose the menu option File>Write VCD>For Selected Variables . The Write VCD For Selected Variables dialog box is displayed.

By default, the Start Time and the End Time are the start and end times of the simulation data saved in the SST2 Database. You can enter your own Start Time and End Time to generate a VCD with a smaller time range.

By default, the "Output VCD File Name" is signalscan.dump . You can change the name of the file by editing it, or by selecting a file from the file browser and overwriting that file. Click on the OK button to perform the translation. To cancel the translation operation, click on the Cancel button. The dialog box goes away without executing the translation.

To save all variables to a VCD file, select File>Write VCD>For All Recorded Variables from the menu.

Limitations

The VCD Writer has the following limitations:

· Strength information is not saved in the VCD file.
· Undefined variable values are saved as X in the VCD file.
· The conversion starts from the time that all the selected variables are recorded.

Buses and Bus Templates

Bus templates allow you to collapse variables with similar names into user-defined buses. This feature is most useful when you are looking at a synthesized schematic, in which a bus has been broken into scalar signals by the synthesis tool. The Bus Template feature can be used in the Design Browser Window.

Bus Template Syntax

Table 5-1 below describes the syntax used to create Bus Templates.

Table 5-1. Bus Template Syntax
Syntax	Description
x and y are any positive integral values When direction is ambiguous, bus(es) are created in ascending order.
busname `[` x `:` y `]`	Generates a bus with a range of x to y . It can be in either ascending or descending order, depending on whether x is less than or greater than y .
busname `[*<` x `]`	Attempts to find consecutive bits less than x and create a bus in ascending order.
busname `[*>` x `]`	Attempts to find consecutive bits greater than x and create a bus in descending order.
busname `[` x `:*]`	Creates a bus in ascending order from x to the highest contiguous signal available.
busname `[<]` or busname `*`	Collapses all signals that have a name of the form busname followed only by digits. All buses formed are in ascending order.
busname `[>]`	Collapses all signals that have a name of the form busname followed only by digits. All buses formed are in descending order.
`` or ` [:]`	Creates all possible buses for signals that satisfy the Bus Template rules. All buses formed are in ascending order.
`[>*]`	Creates all possible buses for signals that satisfy the Bus Template rules. All buses formed are in descending order.
`!` busname `[` x `:` y `]`	Prevents the use of the bits specified in the creation of buses. This option must be preceded by one or more of the above-mentioned Bus Template options, and must be separated from the previous option by a space.

NOTE: Multiple expressions may be used to describe the bus template search pattern. To do so, separate the expressions with spaces.

Bus Template Examples

Assume that a scope of a design consists of only the following variables: mybus1 , mybus2 , mybus3 , mybus4 , mybus5 , mybus6 , mybus7 , mybus8 , mybus9 , and mybus10 .

If you type the following text in the Bus Template Field in the Design Browser Window:

mybus[1:10] !mybus[4]

The following buses are created:

mybus[1:3] mybus[5:10]

If you type the following text in the Bus Template Field:

*[*:*]

The following bus is created:

mybus[1:10]

Create/Modify Bus Dialog

The Create/Modify Bus dialog box shows the components of a bus if one is selected, or allows you to create your own bus from selected variables.

The first field shows the name of the bus. The msb and lsb are then displayed. The Flip Contents button allows you to invert the contents of the bus.

Create a Bus

1. Select the variables you want to group.
2. Select the Edit>Create>Bus menu option.

If all the variables selected have the same name and the trailing bit numbers are consecutive, the default name is the common name, and the indices are from the first and last variables.

You can modify the content of the bus by changing the msb and the lsb and/or flipping the contents of the bus. If not all of the selected variables have a common name (a bundle), the default name is a comma-separated concatenation of the names of the selected variables. When you change the content of the bundle, the default name also changes to reflect its new content.

Change the Name of the Bus

Selecting the New Name button displays a text field where you can specify the new name. You can also specify whether you want the bus name to be displayed with or without indices and the values of the indices.

Use the checkbox to enable or disable the display of indices. Change the value of the indices displayed by editing the msb and lsb fields. The number of bits is enforced, so if you change the msb, the lsb also is changed to reflect the correct bit count.

Note that changing the msb and lsb in the Name section affects only the name of the bus created and not its contents.

The dialog box also has a check box for you to choose between adding the new bus at the insertion point in the Names Pane or replacing the selected variable(s) with the new bus. If you selected the Replace Original checkbox, the selected variables in the Names Pane are deleted when the new bus is added.

Modify a Bus

1. Select either a user-defined bus or a Verilog bus.
2. Choose the Edit>Modify menu option in the Waveform Window or Source Code Window.

The dialog box that appears looks slightly different from the Create Bus dialog box. The name and indices of the original bus are displayed at the top of the window.

To modify the bus, change the bits referenced from the original bus. The default name is the original name with the new modified indices. To rename the bus, select the New Name button in the dialog box.

Using the Register Window

The Register Window allows you to create customized views of your design. Each of these views is called a Register Page. Figure 5-1 shows a Register Page in a Register Window:

Figure 5-1. Register Window and Register Page

You can create your own register pages, and view any variables on any page. You can also move the variables and their values around to make a page more readable.

Creating a Register Page

In the Waveform Window, Source Code Window, or Schematic Tracer Window:

1. Select one or more variables.
2. Select the Edit>Create Register Page menu option.

A dialog box is displayed asking for the name of the register page to be created.

3. Enter the name of the register page and click OK .

The register page is created and is displayed in the Register Window.

Additional variables may be added to the register page using cut and paste.

Selecting Text and Values

In selection mode (using the arrow mouse pointer), use the left mouse button to select text and variable values. Hold down the Ctrl key while clicking to select multiple items.

Normally, a variable and its value are grouped together so that they can be easily moved together. To select individual items from a group, first select Edit>Ungroup Registers to ungroup the items. You can group selected items together by selecting Edit>Group Registers .

Moving Text and Values

In selection mode (using the arrow mouse pointer), you can use the left mouse button to drag selected items to any position on the register page.

Adding Text

In text mode (using the A mouse pointer), click in an unused area of the register page. A text box is displayed. Type in the desired text, and press Return or Enter .

Modifying Text

If the text is in a group, use the Edit>Ungroup menu option to ungroup it. In text mode (using the A mouse pointer), click on the text you want to change. A text box is displayed for you to modify the text.

Viewing a Different Register Page

Click on the desired register page name in the Multi-List Pane on the right side of the display area.

Deleting a Register Page

Click on the register page name in the Multi-List Pane on the right side of the display area. The register page name is highlighted. Use the Delete button, or select Edit>Delete to delete the selected register page.

Multiple Register Windows

To open up a new Register Window, select the Windows>Register menu item from any of the Signalscan windows.

View-Only and Edit Modes

To toggle between View-Only and Edit modes, click on the Lock/Unlock graphical icon located above the vertical scrollbar in the Register Pane in the Register Window.

If you are in View-Only mode, the menu bar and other less used controls are hidden. In addition, the register pane switches to a read-only mode, and you cannot modify the register page in that window. However, if you modify the register page in another Register Window or from the command line, the changes are reflected in all Register Windows, including the ones in View-Only mode.

Next or Previous Variable Change

To jump to the next or previous variable change, select either the >>| or the |<< graphical button. You can also select the Control>Variable Change>Next or the Control>Variable Change>Previous menu item. If no variables are currently selected, Signalscan finds the next or previous change for any of the variables in the register page. If multiple variables are currently selected, Signalscan finds the next or previous change for any of the selected variables.

$reset Support

You can use the Verilog command $reset either by placing it in the Verilog code or by typing it at the Verilog simulator prompt when the simulator is running interactively.

The syntax is:

$reset;

To achieve the same functionality in Signalscan, select the File>Reset Simulation menu option in the Control Window. A dialog box pops up with three options:

· Replace data from the last simulation with new data.

Replaces data recorded before the $reset command with data generated after the $reset . This is the default.

· Copy data from the last simulation and replace with new data.

Similar to the first option except that the data recorded before the $reset is copied before being replaced. Any groups containing data that will be replaced are copied, and the original group contains the newest simulation data.

· Keep data from the last simulation.

Causes no change to what is displayed. Data recorded before the $reset continues to be displayed, but variables from after the $reset may be added to the display manually.

Using the $reset task from Verilog will always cause the old data to be replaced with the new data.

Multi-Stream Simulation Support

You may run Signalscan with connections to as many Verilog simulators as you like. You can either start Signalscan from one of the simulators and have the others connect to the running Signalscan, or you can start Signalscan manually or by some other means, and then have all of the simulators connect to the running Signalscan. In the first case, the simulator that starts Signalscan is the master, and controls like continue and pause will go to that simulator. In the second case, all simulators are peers. In all situations, Signalscan can only control one simulator. The progress control of the other simulators must be handled by other means (such as manually or simulation backplane).

Use the $signalscan task to start Signalscan from a simulator. You can specify an optional string argument listing options to be passed to Signalscan on startup. Signalscan is started on the display indicated by the DISPLAY environment variable. As usual, the $recordvars task should also be used to record some variables to the SST2 Database. Each simulator writes to its own SST2 Database.

Use the $signalscanconnect task to connect to a running Signalscan. The DISPLAY environment variable is used to find a running Signalscan and connect to it. If multiple Signalscans are running on the same display, it selects the first one that it finds. If no Signalscan that accepts incoming connections is currently running, the $signalscanconnect task waits until there is one available. This avoids timing problems where Signalscan is started at the same time simulators are trying to connect.

Vertue, a Bridge Between Verilog and Epic

Vertue is a special environment for multi-stream simulation support. The Vertue system is made of a Verilog simulator connected to an Epic simulator through a Precedence simulation backplane, providing connection and synchronization between the simulators. Signalscan provides control to the Verilog simulator acting as master.

The following steps are required to run Vertue with Signalscan:

· Make sure epic-to-sst is in your executable path.
· Add the following line to your Epic configuration file:

output_filter epic-to-sst -connect

· Create a Do-File to extract the SimMatrix partitioning information using the commands described in "Multi-Stream Simulation Support". An example Do-File, vertue.do , which assumes one Verilog partition and one Epic partition, is shown below:

wait for design verilog.sst; wait for design epic.sst;

stop;

gen simmatrix dofile vertuep.do \

verilog@localhost:1 verilog.sst \

vertue@localhost:1 epic.sst

execute do vertuep.do

· Add the following lines to your Verilog design file:

$recordvars;

$signalscan("-do vertue.do");

Commands for Multi-Stream Simulation Support

define design

def[ine] design design-name [ scope-mapping-list ]

scope-mapping-list ::=

scope-mapping-pair [ scope-mapping-list ]

scope-mapping-pair ::=

( dest-scope-name src-scope-name ) |

(`(` dest-scope-name src-scope-name `)')

Use this command to specify a user-defined design view, which is useful for putting a design back together after it has been partitioned. The design view is created if it does not already exist.

The dest-scope-name is the name of the scope in the design to be defined, and the src-scope-name is the name of the source scope. Each scope-mapping-pair declaration includes any sub-scope (or sub-hierarchy) of the specified src-scope-name . To delete the design, use the close sim command. To remove a particular scope from the design, define that scope to the <VOID>:: scope .

Example

Create a new design called RealDesign that is basically the same as verilog.sst , but uses the scope x.y from epic.sst for top.a , and the scope from verilog.sst for top.a.b .

define design RealDesign \

/ verilog.sst:: \

top.a epic.sst::x.y \

top.a.b verilog.sst::top.a.b

define design RealDesign \

(/ verilog.sst::) \

(top.a epic.sst::x.y) \

(top.a.b verilog.sst::top.a.b)

hide

hide design design-list

design-list := design-name [ design-list ]

This command "hides" a design so that it is not visible in the list of designs above the top level scopes.

reveal

reveal design design-list

design-list := design-name [ design-list ]

This command "reveals" a design that has been previously hidden.

gen[erate]

gen[erate] simm[atrix] [desi[gn] design-name ] do[file] dofile-name

[ simmatrix-list ]

simmatrix-list ::= simmatrix-pair [ simmatrix-list ]

simmatrix-pair ::=

( solver sst-filename ) | (`(` solver sst-filename `)')"

This command generates a Do-File from a design running under the Precedence simulation backplane SimMatrix (Vertue, for example). The simulator(s) must be connected to Signalscan and must be stopped while using this command. This command will only work if the simulators are running under SimMatrix control. The following example Do-File, vertue.do , illustrates this command:

veture.do --

gen simmatrix dofile vertuep.do \

verilog@localhost:1 verilog.sst \

vertue@localhost:1 epic.sst

execute dofile vertuep.do

The above Do-File generates and executes another Do-File called vertuep.do in which it specifies a user-defined design and hides both of the partitioned designs.

Mnemonic Mapping

The purpose of this feature is to map the values of a bus to a set of mnemonic symbols.

Mnemonic mappings are created, edited, and deleted in the Define Mnemonic Mapping dialog box. Select the Option>Define Mnemonic Mappings menu option, available in every Signalscan window, to display this dialog box. Initially, the Mnemonic Map Name field contains a default name, and the Value and Mnemonic panes contain one mnemonic value pair that maps default to <`h> (hexadecimal display).

To view a list of defined mnemonic maps, click on the down arrow button of the Mnemonic Map Name drop-down list. When you select a mnemonic map from the mnemonic map name list, the contents of that mnemonic map are displayed in the Value and Mnemonic panes. You can modify a mnemonic map name by simply typing a new name in the Mnemonic Map Name field.

Use the New Map button to create a new mnemonic map. A default name is supplied for the newly created mnemonic map. The Value and Mnemonic panes initially contain one mnemonic value pair that maps default to <`h> .

Use the Delete Map button to delete an existing mnemonic map. The current mnemonic map shown is deleted from the mnemonic map list. The next available mnemonic map in the list is shown. If there is no next map, the previous available mnemonic map in the list is shown.

The mnemonic value pairs for a mnemonic map are shown in the Value and Mnemonic panes. The pairs are sorted by value. For each bit of the value, the sequence is "0", then "1", then "?". The last mnemonic value pair has the value default , and matches any value not matched by any other value in the map. You cannot have more than one pair with the same value.

Radix is used to set the default radix for entering and displaying the values in the Value Pane. The default is hexadecimal but you can change it to one of the values listed in Table A-1. If you want to enter the data in a different radix format, prefix the value with the appropriate prefix as shown in the table.

Once you hit Return or Tab , the value is converted to the default radix. If it is not possible to convert, the value is displayed in binary with the prefix `b .

The mnemonic is a string of printable characters that may optionally contain a replacement specification. The replacement specification may be <`b> , <`o> , <`d> , <`s> , <`h> , or <`a> . The replacement specification is replaced by the actual value in the corresponding format.

Click on any mnemonic or value item to modify its content. A cursor appears so that you can edit the field. If you change the value, the mnemonic value pair is moved to the proper position in the list.

To add a mnemonic value pair to the current mnemonic mapping, click in the Value Pane below the Default entry. A cursor appears so that you can enter the new value. Next, press the Tab key or click in the Mnemonic Pane to enter the corresponding mnemonic. When you are finished, press Tab or Return , and the new mnemonic value pair is moved to the proper position in the list.

To select one or more mnemonic value pairs, select the numbers on the left side of the Value Pane. The selected items may be cut, copied, or deleted by clicking on the appropriate button. The default mnemonic value pair cannot be deleted.

Cut, Copy, and Paste operations are applied only within the dialog box and can be used to move or copy the mnemonic value pairs between any mnemonic mappings. Pasted entries are automatically sorted and placed in the proper position.

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DAI Signalscan User's Guide

CHAPTER 5 Advanced Features

VCD Writer