© 1996-1999 Design Acceleration, Inc. All rights reserved.
DAI Signalscan Version 6.2, February 12, 1999.
This document contains proprietary and confidential information of Design Acceleration, Inc. (DAI). No part of this manual may be copied, transmitted, or transcribed without the prior written consent of DAI. All information contained herein shall be used strictly in accordance with the terms of the written non-disclosure agreement. Your right to copy DAI software and this publication is limited by copyright law and your end user license agreement.
The information in this manual is subject to change without notice and in no event shall DAI be liable for any loss whatsoever resulting from any change or error in this publication or in the software.
Trademarks
The DAI logo, DAI Signalscan, DAI Signalscan Pro, DAI Signalscan TX, Transaction-Based Verification, TBV, Transaction Viewing, DAI Checkbench TX, Cause Finder, DAI SST2 Database, DAI Coverscan, DAI Comparescan, and DAI Statescan are trademarks of Design Acceleration, Inc.
Verilog-XL is a registered trademark of Cadence Design Systems, Inc.
All other products and trademarks are the property of their respective owners.
