DAI Comparescan User's Guide
The DAI Comparescan Tutorial

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The DAI Comparescan Tutorial

Using DAI Comparescan

The sample simulation files, golden.sst and test.sst were generated directly from the simulator using DAI's PLI routines. We recommend that you use SST files generated by the simulator since it will contain port information, which is not available through the VCD files.

Detailed instructions for linking the Design Accleration PLI to your Verilog simulator are available in the chapter on "Interfacing DAI Comparescan to your Verilog Simulator".

Starting DAI Comparescan

comparescan

The DAI Comparescan window is displayed. Compare errors and messages will be displayed in this window.

Specifying the files for comparison

1. click on the Options button.

A dialog box is displayed for you to specify the files to compare and set various other options. (See figure 4.2 below.)

2. click on the Browse button next to the "Golden File" label.

Another dialog box is displayed for you to browse and select files.

3. double click on golden.sst.

This will specify golden.sst to be used

4. click on the Browse button next to the "Secondary File" label.

5. when the "File Select" dialog box comes up, double click on test.sst.

6. click on the OK button at the bottom of the dialog box

Running the comparison

To start the comparison: click on the Run button in the window.

You can see the Design Acceleration icon animated while the comparison is in progress. The bottom of the window also show the current signals or scopes being processed.

The comparison is finished when the animation stops and the status at the bottom of the window says "Compare Complete. Processed ..."

Interpreting the messages and errors

Additional information on the rules used to comparison are listed on the next couple lines. The first Info line tells us that no rule was specified for the comparison so the default rule will be used. The second Info line shows that the default rule is to compare the top scope for one level of hierarchy and compare the internal signals as well as the ports. The default rule also limits the number of errors per signal to 50.

Under the info lines are two error messages. They indicate that two variables has matching names but has different number of bits, so no comparison was performed.

Beneath the error message is the list of the scopes which have errors. The letter "M" in front of the scopes indicate that they are modules. Variables will have the waveform sign in front of them.

Scope hello has 5 errors and scope top has 79 errors.

View the errors and messages in Hierarchy View

1. click on the scope name hello.

This will list the signals under that scope. To the left of the signal name is the number of errors for that signal.

2. click on the variable o1.

The list of time and error type is displayed under the variable. For this signal, there are 5 points in time when there are mismatches. (See Figure 4 below)

View the error and messages in Time View

To view the errors sorted by time:

1. click on the TimeView button.

This will change the information in the window. Instead of the design hierarchy, the window now lists all the errors for all of the signals sorted by time. The summary, info and error message still are listed first. But under those are all the errors. In this example, the first error is at time 0 for signals hello.o1.

2. click on the H-View button.

This changes the window back into hierarchy view.

Viewing the errors with DAI Signalscan

To invoke DAI Signalscan and view the errors:

1. Show the errors for signal top.s1.

The first mismatch is between 1.43ns and 1.54ns, the second mismatch is between 3.4ns and 3.51ns.

2. Double click on the second error

A dialog box is displaying indicating that DAI Signalscan is being invoked. DAI Signalscan will then come up and the top.s1 from each file will be added into the Waveform Window. Cursor1 and cursor2 will mark the area of error between time 3400ps and 3510ps. (See Figure XXX)

3. Click on the Next button to see the error between time 5370ps and 5480ps.

Viewing other errors with DAI Signalscan

1. Expand signal top.s3

2. Double click on the second error under s3. DAI Signalscan will add top.s3 from each file and position cursor1 and cursor2 around the area of mismatch.

Using a rules file for comparison

Let's run the comparison again, this time, comparing only certain signals or scopes. We will be using the demo.rules file which has examples of most of the options available in DAI Comparescan. The content of the file is listed below:

datafile1 golden.sst

datafile2 test.sst

compare top.golden top.s1

compare top.golden top.s2 -start 500 -tol 50

clkdef clk1

clkcompare clk1 top.golden top.s3

clkcompare clk1 top.golden top.s4 -posedge -tol 3

stability clk2 top.goodBus

clkdef clk3 top.c3 -setup 20 -hold 20

stability clk3 top.bus1

clkcompare clk2 top.goodBus clk3 top.bus1 -tol 3 \

when "(top.bus1 | 3'b001) || (top.goodBus==2)"

// clock compare for entire module

clkdef clk4 top.d1.clk

clkcompare clk4 hello.d1 -internal -depth 3

The first two lines specify the golden file and secondary file, respectively. The rest of the commands are compare commands.

DAI Comparescan supports two types of comparisons, absolute compare and clocked compare. Absolute compare will find all the difference between the two signals at any point in time, where clock compare will only check on the clock edges.

Clocked compare is much faster then absolute compares and is more commonly used. compare does absolute compares and clkcompare does clocked compares.

These two commands can take optional flags, such as -start and -end, which specifies when to start and stop the comparison. The -tol, -pos and -neg flags can be used to specify the window of tolerance for comparison, where -pos speifies the positive tolerance (amount of time before the edge), -neg specifies the negative tolerance (the amount time after the edge), and -tol specifies both the positive and negative tolerance.

Clkcompare requires an additional signal to be used as the clock. By default, the comparison will be on the rising edge (-posedge), but the user can change the comparison be on the falling edge or both edges with the -negedge or -bothedge flags, respectively.

Clkcompare can additionally take optional flags for setup and hold times to check against the clock. If these parameters are set, setup and hold time for the signals are automatically checked.

Should the user only care about checking for setup and hold violations without comparisons, the stability command can be used.

The when option can be added to the compare statements to qualify errors. Only when the expression of the when option evaluates to true are the errors reported.

NOTE: Rules and options specified in the rules file will override those in the Options Dialog Box.

A more complete list of commands, options and explanations can be found in the Rules File chapter of the User's Guide.

To use this rules file:

1. Click on the Options button.

This will bring up the options dialog box.

2. Click on the Browse button next to the "Rules file:" label.

3. Double click on the file name demo.rules to use it.

4. Click on the OK button.

5. Click on the Run button to start the comparison using this rules file.

Using new rules file and simulation files for comparison

1. Click on the Options button.

This will bring up the options dialog box

2. Click on the Browse button next to the "Rules file:" label.

3. Double click on the file name entire_design.rules to use it.

This rules file will compare all matching signals in each simulation file.

4. Click on the OK button.

5. Click on the Run button to start the comparison using the new rules file.

Exiting DAI Comparescan

1. Select "File->Exit".

2. Click the OK button when prompted.

Summary

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