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Document Version 1.7
For UNIX Platforms
January 31, 1997
This document contains proprietary and confidential information of Design Acceleration Inc. No part of this manual may be copied, transmitted, or transcribed without the prior written consent of Design Acceleration. All information contained herein shall be used strictly in accordance with the terms of the written non-disclosure agreement. Your right to copy Design Acceleration software and this publication is limited by copyright law and your end user license agreement.
The information in this manual is subject to change without notice and in no event shall Design Acceleration Inc. be liable for any loss whatsoever resulting from any change or error in this publication or in the software.
Trademarks
DAI Signalscan, DAI Signalscan Pro, DAI Comparescan and Design Acceleration are trademarks of Design Acceleration, Inc.
Verilog and Verilog-XL are registered trademarks of Cadence Design Systems, Inc.
All other products and trademarks are the property of their respective owners.
Design Acceleration Inc. Design Acceleration Europe
2105 Hamilton Avenue Leigh Court
Suite 370 Abbots Leigh
San Jose, CA 95125 USA Bristol BS8 3RA U.K.
Phone: (408) 559-8500 Phone: (+44) (0) 1275 374831
Fax: (408) 371-5196 Fax: (+44) (0) 1275 374828
Web site : http://www.designacc.com
Email info@designacc.com
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